Picocom Chief Architect wins RISC-V International Award
RISC-V E-Trace Ratification Award Win
At the RISC-V Summit 2022 in San Jose, Picocom’s Chief Architect Gajinder Panesar (pictured 3rd from left in the awardees group photograph) was presented with the RISC-V Ratification Award for ratifying Efficient Trace (E-Trace) for RISC-V this year.
At Embedded World in June 2022, RISC-V International announced a new batch of specifications detailing extensions and standards, which can be added to the RISC-V instruction set architecture — the first to be ratified so far this year.
E-Trace for RISC-V defines a highly efficient approach to processor tracing that uses a branch trace, ideal for debugging any type of application from tiny embedded designs to super powerful computers. E-Trace for RISC-V documentation specifies the signals between the RISC-V core and the encoder (or ingress port), a compressed branch trace algorithm, and a packet format to encapsulate compressed branch trace information.
Gajinder Panesar of Picocom and Chair of the RISC-V’s E-Trace Task Group, which led the development and ratification of this specification. The E-Trace specification was the first of the four specifications RISC-V International has formally ratified — adding to the 16, representing over 40 individual extensions, ratified in 2021.
The E-Trace specification defines a standard mechanism for accessing trace information from a RISC-V platform. Like the RISC-V ISA, the specification defines the interface rather than the implementation, allowing the designer to optimise a particular implementation.
For more information on the RISC-V International, click here.